Arithmetic logic units use banks of multipliers to perform logic operations. When generating the product of two binary numbers, each multiplier forms a plurality of partial products which, first, are compressed for space and processing efficiency and, then, are added to form the final product of the two numbers. Compression of the partial products is the most significant operation in the multiplier in terms of delay and power.
In many multiplier circuits, full adder blocks are used to compress the partial products prior to their summation. These blocks (known as 3:2 and 4:2 compressors) are power inefficient and slow, especially when large bit numbers are multiplied. This is because the delay time for obtaining the product increases linearly with bit length.